This invention relates to an integrated silicon circuit for providing signal delay including a PN-junction capacitor and more particularly to such a circuit wherein the capacitor, after being charged to nearly the full power supply voltage, must be almost completely discharged to terminate the delay period.
It is known to employ a resistor-capacitor combination wherein the capacitor is either charged or discharged as an exponential function of time. Such timing or delay circuits usually require the use in a trigger circuit of a threshold voltage that is intermediate the potentials of the two DC power supply busses, and the capacitor is therefore not fully discharged (or charged) at the time of turning on the trigger circuit and terminating the delay period.
It is an object of this invention to provide in a simple low cost integrated circuit a signal delay means wherein the amount of delay is substantially independent of severe drops in power supply voltage during the delay period.